With the development of semiconductor technology, the requirements for packaging integrated circuits have becoming stricter. Currently, most of the high pin-count chips (such as graphic chips and chip sets, etc.) are packaged by a BGA (Ball Grid Array) technique, wherein the BGA technique can be divided into five categories including a PBGA (Plastic BGA) substrate, a CBGA (Ceramic BGA) substrate, a FCBGA (FlipChip BGA) substrate, a TBGA (Tape BGA) substrate, and a CDPBGA (Carity Down PBGA) substrate. The FCBGA technique is to dispose Au or solder bumps on an IC chip for soldering to a printed wiring board (PWB).
For example, referring to FIG. 1, FIG. 1 is a schematic cross-sectional view showing the structure of a conventional solder bump prepared by a film electro-deposition process. Such as shown in FIG. 1, a silicon wafer 100 includes a conductive pad 12, a passivation layer 110, a conductive layer 180 and a solder ball 190. The conductive pad 102, such as an aluminum pad or a copper pad, is used for forming an electrical connection to an external circuit (not shown). The passivation layer 110 is used for providing a semiconductor structure with protection and a planarization surface, wherein the passivation layer 110 allows the surface 102a of the conductive pad 102 to be exposed. The conductive layer 10, such as a UBM (Under Bump Metallurgy Layer) layer formed by sputtering, covers a portion of the passivation layer 110 and the surface 102a of the conductive pad 102. The UBM layer is typically composed of an adhering/diffusion barrier layer 160 and a wetting layer 170, for increasing the adhesion between the solder ball 190 and the conductive pad 102.
Referring to FIG. 2A to FIG. 2D, FIG. 2A to FIG. 2D are schematic cross-sectional views showing the process for making the passivation layer 110 shown in FIG. 1. At first, such as shown in FIG. 2A, a silicon wafer 100 is provided, wherein the silicon wafer 110 has a plurality of conductive pads 102 formed thereon. Then, such as shown in FIG. 2B, a passivation layer 110 is coated on the silicon wafer 100 so as to cover the conductive pads 102, wherein the passivation layer 110 is made of polyimide, and the thickness thereof is about 10 μm. Thereafter, such as shown in FIG. 2C, an exposure/develop step is performed to form a plurality of openings 112 on the passivation layer 110 for exposing the conductive pads 102. Then, such as shown in FIG. 2D, a baking step is performed for curing the passivation layer 110. In the conventional skill, since the passivation layer 110 is formed by only one costing step and covers the entire surface of the silicon wafer 100, a particle 104 (shown in FIG. 2A) if existing on the silicon wafer 100 will easily result in a void 114 (shown in FIG. 2D) formed on the surface of the final passivation layer 110, wherein the existence of the void 114 will easily cause customer complaints and lower the product yield.